? products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron?s production data sheet specifications. x16 addendum micron technology, inc., reserves the right to change products or specifications without notice. mt48lc8m16a2_addendum.fm - rev. 7/02 1 ?2002, micron technology inc. 128mb x16 sdram addendum preliminary ? synchronous dram mt48lc8m16a2 ? 2 meg x 16 x 4 banks for the latest data sheet, please refer to the micron web site: www.micron.com/dramds features ? supports pc100 and pc133 functionality fully synchronous; all signals registered on positive edge of system clock internal pipelined operation; column address can be changed every clock cycle internal banks for hiding row access/precharge programmable burst length s: 1, 2, 4, 8, or full page auto precharge, includes concurrent auto precharge, and auto refresh modes self refresh mode; standard and low power lvttl-compatible inputs and outputs single +3.3v 0.3v power supply 64ms, 4,096-cycle refresh part number: MT48LC8M16A2TG-6A addendum changes the standard 128mb sdram data sheets also per- tain to the x16 device and should be referenced for a complete description of sdram functionality and operating modes. however, to meet the faster speed grades, some of the ac timing parameters are slightly different. this addendum data sheet will concentrate on the key differences required to support the enhanced speeds. the micron 128mb data sheet provides full specifi- cations and functionality unless specified herein. option marking configuration 8 meg x 16 (2 meg x 16 x 4 banks) 8m16 write recovery ( t wr) t wr = ?2 clk? 1 note: 1. refer to micron technical note: tn-48-05. a2 package plastic package ? ocpl 2 2. off-center parting line. 54-pin tsop ii (400 mil) tg timing (cycle time) 6.0ns @ cl = 3 -6a self refresh standard none operating temperature range commercial (0 o c to +70 o c) none 8 meg x 16 configuration 2 meg x 16 x 4 banks refresh count 4k row addressing 4k (a0?a11) bank addressing 4 (ba0, ba1) column addressing 512 (a0?a8) key timing parameters speed grade clock frequency access time cl = 3* setup time hold time -6a 167 mhz 5.4ns 1.5ns 0.8ns
128mb x16 sdram addendum preliminary x16 addendum micron technology, inc., reserves the right to change products or specifications without notice. mt48lc8m16a2_addendum.fm - rev 7/02 2 ?2002, micron technology inc. i dd specifications and conditions notes: 1, 5, 6, 11, 13; notes appear in the standard data sheet; v dd /v dd q = +3.3v 0.3v parameter/condition symbol -6a units notes operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd1 170 ma 3, 18, 19, 32 standby current: power-down mode; all banks idle; cke = low i dd2 2ma32 standby current: active mode; cke = high; cs# = high; all banks active after t rcd met; no accesses in progress i dd3 50 ma 3, 12, 19, 32 operating current: burst mode; continuous burst; read or write; all banks active i dd4 165 ma 3, 18, 19, 32 auto refresh current cke = high; cs# = high t rfc = t rfc (min) i dd5 330 ma 3, 12, 18, 19, 32, 33 t rfc = 15.625s i dd6 3ma self refresh current: cke 0.2v standard i dd7 2ma4
128mb x16 sdram addendum preliminary x16 addendum micron technology, inc., reserves the right to change products or specifications without notice. mt48lc8m16a2_addendum.fm - rev 7/02 3 ?2002, micron technology inc. electrical characteristics and recommended ac operating conditions notes 5, 6, 8, 9,11; notes appear on in the standard data sheet ac characteristics -6a parameter symbol min max units notes access time from clk (pos. edge) cl = 3 t ac(3) 5.4 ns 27 address hold time t ah 0.8 ns address setup time t as 1.5 ns clk high-level width t ch 2.5 ns clk low-level width t cl 2.5 ns clock cycle time cl = 3 t ck(3) 6ns23 cke hold time t ckh 0.8 ns cke setup time t cks 1.5 ns cs#, ras#, cas#, we#, dqm hold time t cmh 0.8 ns cs#, ras#, cas#, we#, dqm setup time t cms 1.5 ns data-in hold time t dh 0.8 ns data-in setup time t ds 1.5 ns data-out high-impedance time cl = 3 t hz(3) 5.4 ns 10 data-out low-impedance time t lz 1ns data-out hold time (load) t oh 3ns data-out hold time (no load) t oh n 1.8 ns 28 active to precharge command t ras 42 120,000 ns active to active command period t rc 60 ns active to read or write delay t rcd 18 ns refresh period (4,096 rows) t ref 64 ms auto refresh period t rfc 60 ns precharge command period t rp 18 ns active bank a to active bank b command t rrd 12 ns 7 transition time t t 0.3 1.2 ns write recovery time 1 t wr 1 clk + 6ns ns 12 ns 25 exit self refresh to active command t xsr 67 ns 20 note: 1. auto precharge mode only. the precharge timing budget ( t rp) begins 6ns for -6a after the first clock delay, after the last write is executed. may not exceed limit set for precharge mode.
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.m icron.com, customer comment line: 800-932-4992 micron and the m logo are registered trademarks and the micron logo is a trademark of micron technology, inc. 128mb x16 sdram addendum preliminary x16 addendum ?2002, micron technology inc. mt48lc8m16a2_addendum.fm - rev 7/02 4 data sheet designation preliminary: this data sheet contains initial charac- terization limits that are subject to change upon full characterization of production devices. ac functional characteristics notes appear in the standard data sheet. parameter symbol -6a speed units notes read/write command to read/write command t ccd 1 t ck 17 cke to clock disable or power-down entry mode t cked 1 t ck 14 cke to clock enable or power-down exit setup mode t ped 1 t ck 14 dqm to input data delay t dqd 0 t ck 17 dqm to data mask during writes t dqm 0 t ck 17 dqm to data high-impedance during reads t dqz 2 t ck 17 write command to input data delay t dwd 0 t ck 17 data-in to active command t dal 5 t ck 15, 21 1 data-in to precharge command t dpl 2 t ck 16, 21 last data-in to burst stop command t bdl 1 t ck 17 last data-in to new read/write command t cdl 1 t ck 17 last data-in to precharge command t rdl 2 t ck 16, 21 load mode register command to active or refresh command t mrd 2 t ck 26 data-out to high-impedance from precharge command (cl=3) t roh(3) 3 t ck 17 note: 1. the note 21 in the standard data sheet does not apply for this speed grade and should read ?based on t ck = 6ns?
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